For advanced CMOS technology nodes, middle of line (MOL) patterning utilizes extreme ultraviolet (EUV) lithography because contact pitch is so small and it also avoids misalignment error due to multiple color patterning. However, current patterning schemes still print source/drain contacts (CAs) and gate contacts (CBs) separately, because reactive ion etching (RIE) for CAs has different requirements from RIE for CBs, and two expensive EUV masks are required. First, CA RIE only etches oxide and needs to be selective to gate cap material (e.g. silicon nitride (SiN)) to avoid a CA to gate (PC) electrical short. Secondly, CB RIE needs to open the gate cap to make contact to the PC.
FIG. 1 shows a top view of a semiconductor device including a PCs 101 formed over an active region 103 including source/drain (S/D) regions on sides of the PCs 101. CAs 105 are formed over the active region 103, and a CB 107 is formed over the PC 101.
A need therefore exists for methodology enabling concurrent formation of CAs and CBs with a single mask and the related device.